1. Field of the Invention
The invention relates to a package structure, and more particularly, to a package structure capable of achieving greater reliability and production yield.
2. Description of the Prior Art
In the semiconductor industry, the production of integrated circuits is generally divided into two stages: integrated circuit manufacturing and integrated circuit packaging. The manufacturing of integrated circuit includes processes such as wafer manufacturing, circuit design, photomask manufacturing, and wafer dicing. Integrated circuit packaging on the other hand, includes processes such as wire bonding or flip chip assembly for electrically connecting a circuit chip to a substrate or a lead frame.
As the demand of smaller, more functional and complex PDAs, cellular phones, CPUs, and memory modules increases each day, the development of semiconductors also moves toward a direction of higher density packaging. Among many popular package structures, a flip chip (FC) structure with the characteristics of rapid cooling, low inductance, multi-terminal, and small size has been used most commonly in favor of others. In general, a flip chip package involves formation of a plurality of bumps on a chip and the addition of a layer of solder paste on the lead frame. The chip is then attached to the lead frame by melting the paste via a reflow process. Essentially, this type of package structure has already been disclosed in U.S. Pat. No. 6,661,087. Nevertheless, the reflow process often causes the melting-state chip bumps and the solder paste to travel on the lead frame, which eventually causes the chip to move away from its original position and result in problems such as product failure or low production yields.
In the recent history of integrated circuit packaging, passive devices (i.e. electrical resistors, capacitors, or inductors) have often been used for applications requiring high frequency or various other electrical properties. In the past, passive devices have generally been placed on the surface of printed circuit boards (PCBs). However, in order to reduce the space occupied on the PCB, most passive devices today are integrated into the chip. Eventually, a system in a package (SiP) was formed to provide a high efficiency, low cost, and small size package design for the market.
In the SiP design, the solder paste is often used as a linking medium between the passive device and the lead frame. After being processed by a reflow process via high temperature, the melting solder paste readily bonds the passive device and the lead frame together. Nevertheless, the reflow process often causes the solder paste to travel on the lead frame and the passive device to shift from its original position and results in problems such as product failure or low production yield. Consequently, it becomes a critical matter for the package industry to actively look for a package structure design that is able to effectively prevent the solder paste from moving on the lead frame.